In many modern integrated circuits (ICs), multi-phase clocks are often used for applications such as frequency division (PLLs), ADC and DAC interleaving, N-path filtering, zero-IF downconversion, harmonic rejection receivers and transmitters, switched-capacitor circuits and complex-domain analog signal processing. An example of a divide-by-4 circuit, which generates 4 clock phases, is shown in FIG. 1.
As important building blocks, the power consumption, chip area, phase noise performance, and frequency operating range are key characteristics of clock-generating circuits. Typically, a clock-generating circuit comprises a number of memory elements, such as latches and/or flipflops. These memory elements can be composed of, for example, standard or custom CMOS latches, dynamic transmission gate flipflops (DTGFFs), or current-mode logic (CML) latches with or without inductive load. Examples of these implementations are shown in FIG. 2, FIG. 3, and FIG. 4, respectively.
As can be observed, some flipflops have a differential input and/or differential output, and some use a differential clock. Differential signaling may be preferable in many ICs due to its ability to suppress common-mode disturbances from e.g. supply, ground, or neighboring circuitry.
Differential outputs are naturally available in CML, which can achieve high operating frequencies. However, these flipflops require a static current, and their current consumption is set according to the highest frequency at which they are supposed to operate. This implies a power penalty at lower operating frequencies. The power consumption can be reduced by employing inductors L instead of (or in addition to) load resistors R, see FIG. 4, but this limits the frequency range of operation and is highly prone to undesired magnetic coupling.
Park et al. “A 1.8 V 900 uW 4.5 GHz VCO and Prescaler in 0.18 um CMOS Using Charge-Recycling Technique”, IEEE Microwave and Wireless Components Letts, vol. 19, no. 2, February 2009, discloses sharing the CML-current with the oscillator current to circumvent the additional current, but uses significantly more voltage headroom, more than is typically available in modern CMOS-processes.
Regenerative dividers, such as proposed in Mazzanti et al. “Analysis and Design of Injection-Locked LC Dividers for Quadrature Generation”, IEEE J. Solid-State Circ., vol. 39, no. 9, September 2004, rely on non-linearities combined with a narrowband band-pass filter and feedback to create multi-phase outputs at lower frequencies. However, the creation of narrowband filtering typically uses large inductors with their associated disadvantages, or noisy and power-hungry components defying the power advantage of a regenerative divider.
Dutta et al. “Flip-Flops for Accurate Multiphase Clocking: Transmission Gates Versus Current Mode Logic”, IEEE Trans. Circ. Syst. I, vol. 60, no. 7, July 2013 describes that it can be more power-efficient to generate multi-phase outputs using DTGFFs. For example, for each phase, it can have two transmission gates (TGs) that are driven by a clock, and two inverters which operate rail-to-rail, as illustrated in FIG. 3.